1. Field of the Invention
The present invention relates to solid-state imaging devices, and in particular to a CMOS type solid-state imaging device and a drive method of the solid-state imaging device. The present invention also relates to an electronic apparatus including the solid-state imaging device.
2. Description of the Related Art
Video cameras and digital still cameras are in widespread use. Such a camera includes a charge-coupled device (CCD) solid-state imaging device or an amplified solid-state imaging sensor. The amplified solid-state imaging device guides a signal charge, generated and stored at a light sensing unit of each pixel, to an amplifier, and then outputs a signal, amplified by the amplifier in response to the signal charge, from the pixel. A plurality of such pixels are arranged in a matrix. The amplified solid-state imaging devices also include a solid-state imaging device having junction-type field effect transistors in the amplifier thereof, and a complementary metal oxide semiconductor (CMOS) solid-state imaging device having CMOS transistors in the amplifier thereof.
A typical CMOS solid-state imaging device reads successively on a per row basis a signal charge generated and stored on a photoelectric converter at each of the pixels arranged two-dimensionally in a matrix.
FIG. 1 generally illustrates a CMOS solid-state imaging device 100 of the related art. Referring to FIG. 1, the CMOS solid-state imaging device 100 includes a plurality of pixels 104 arranged on a substrate (not illustrated), vertical drive circuit 111, column signal processing circuit 106, horizontal drive circuit 107, output circuit 108, etc.
The vertical drive circuit 111 is arranged in a region adjacent to one side of a pixel module 117 having a plurality of pixels 104. The vertical drive circuit 111 includes a shift register, for example, and outputs a transfer pulse φTRG, a the reset pulse φRST, and a selection pulse φSEL for selectively scanning the pixels 104 of the pixel module 117 in a vertical direction on a per row basis.
The column signal processing circuit 106 is arranged at the final stage of the vertically aligned pixels 104, i.e., at each vertical column of the pixels 104. The column signal processing circuit 106 performs signal processing operations, including a noise removal operation and a signal amplification operation on the signals output from one row of pixels 104 in response to a signal from a black reference level pixel area (not illustrated but arranged surrounding effective pixels) on a per pixel column basis.
The horizontal drive circuit 107, including a shift register, for example, successively outputs a horizontal scan pulse. The horizontal drive circuit 107 thus successively selects the column signal processing circuits 106 and causes the selected column signal processing circuit 106 to output a pixel signal to a horizontal signal line 114.
The output circuit 108 performs a signal processing operation on signals successively supplied from the column signal processing circuits 106 via the horizontal signal line 114.
The pixel 104 includes a light sensing unit PD having a photodiode, and a plurality of MOS transistors. The pixel 104 here includes four MOS transistors of a transfer transistor Tr1, a reset transistor Tr2, an amplifying transistor Tr3, and a selection transistor Tr4. Optionally, the pixel 104 may include three transistors, i.e., the transfer transistor Tr1, the reset transistor Tr2, and the amplifying transistor Tr3, excluding the selection transistor Tr4.
The transfer transistor Tr1 receives the transfer pulse φTRG via a line 115 from the vertical drive circuit 111. In response to the transfer pulse φTRG, the transfer transistor Tr1 transfers a signal charge stored at the light sensing unit PD to a floating diffusion region FD. The reset transistor Tr2 receives the reset pulse φRST via a line 112 from the vertical drive circuit 111. In response to the reset pulse φRST, the reset transistor Tr2 resets the voltage at the floating diffusion region FD to a voltage close to a power source voltage VDD. A signal voltage responsive to the voltage at the floating diffusion region FD is applied to the gate of the amplifying transistor Tr3 and is thus amplified by the amplifying transistor Tr3. The selection transistor Tr4 receives the selection pulse φSEL via a line 116 from the vertical drive circuit 111. In response to the selection pulse φSEL, the selection transistor Tr4 outputs the signal voltage amplified by the amplifying transistor Tr3 to a vertical signal line 113 as a pixel signal.
Referring to FIG. 1, the CMOS solid-state imaging device 100 includes the vertical drive circuit 111 on one side only of the pixel module. In a pixel 104 far apart from the vertical drive circuit 111 (i.e., a pixel 104 at the side opposite the side having the vertical drive circuit 111), a supplied drive pulse is subject to a delay and a wave deformation because of a wiring resistance and a parasitic capacitance between adjacent wiring lines. As the number of pixels 104 increases (for fine picture), the number of pixels to be driven also increases. The problem of resistance and parasitic capacitance is not ignored. The driving of the pixels 104 at high speed becomes difficult.
As illustrated in FIG. 2, the vertical drive circuits 111a and 111b are arranged on both sides of the pixel module so that the pixels 104 are driven from both sides. As illustrated in FIG. 2, like elements are designated with like reference numerals, and the discussion thereof is omitted.
The solid-state imaging device illustrated in FIG. 2 includes the vertical drive circuits 111a and 111b on both sides of the pixel module 117. The pixels 104 on the left half of the pixel module 117 are driven by the vertical drive circuit 111a arranged on the left side of the pixel module 117 while the pixels 104 on the right half of the pixel module 117 are driven by the vertical drive circuit 111b arranged on the right side of the pixel module 117.
In the arrangement illustrated in FIG. 2, pixels 104 in the center of the pixel module 117 are far apart from the vertical drive circuits 111a and 111b, the drive pulse is subject to delay and waveform deformation. It is difficult to drive the pixel 104s at a high speed.
A concurrent imaging function (global shutter function) has been recently proposed to achieve a concurrent storage of signal charge in a CMOS type solid-state imaging device. The application field of the CMOS solid-state imaging device having the global shutter function has become widespread.
To achieve the global shutter function, the CMOS solid-state imaging device supplies concurrently transfer pulses to all the pixels, and reads concurrently the signal charges from all the pixels. In the solid-state imaging device in the related art, a drive pulse to be supplied to a pixel far apart from the vertical drive circuit is subject to delay and waveform deformation. It is difficult to drive concurrently all the pixels, and if a high-speed operation is performed, pixel blurring takes place.
Japanese Unexamined Patent Application Publication No. 2006-49361 discloses a structure that increases a pixel processing speed. According to the disclosure, a CMOS type solid-state imaging device is connected via a micro bump to a signal processing chip having a signal processing circuit for processing a pixel signal output from the CMOS type solid-state imaging device. In this structure, a pixel far apart from a vertical drive circuit is still subject to pulse delay and pulse deformation, and drive synchronization of the pixels is not achieved.
The pixel module of the solid-state imaging device is configured in an array of rows and columns of pixels. Since the pixel module is configured in an array structure, a circuit for driving pixels and for reading a signal is typically as a cyclic layout pattern circuit that is cyclically repeated in a vertical direction (in a direction of row arrangement) or in a horizontal direction (in a direction of column arrangement) in accordance with the array of pixels.
The cyclic layout pattern circuit is subject to a delay in the timings of activation and deactivation of a signal depending on the pixel position in the vertical direction or the horizontal direction. Such delay is due to a difference in parasitic resistance and parasitic capacitance dependent on a wiring line length, or due to a difference in an IR drop dependent on a distance from a power source. The IR drop is a voltage drop caused along a power source line and determined by the product of a current I and a resistance R.
If a delay takes place in the timings of activation and deactivation of the signal depending on the pixel position in the vertical direction or the horizontal direction, shading and lack of synchronization may take place in the vertical direction and the horizontal direction. To prevent the generation of shading, the activation and deactivation timings are preferably tuned on a per row basis or a column basis.
The parasitic resistance and the parasitic capacitance of the wiring line and the threshold value of each transistor of the cyclic layout pattern circuit vary from chip to chip. The activation and deactivation timings of the signal also vary from chip to chip. An amount of correction for the shading and synchronization also differs from chip to chip.
Without tuning correction on a per chip basis, design specifications are to be determined taking into consideration tailed distribution. Such a consideration is expected to lower production yield. To this end, the activation and deactivation times of the signal on a per chip basis are tuning corrected.
A tuning correction method of a characteristic value of a solid-state imaging device is disclosed in Japanese Unexamined Patent Application Publication No. 2007-208926, for example. In accordance with the disclosure, recommended characteristic information stored on a non-volatile memory arranged on the same chip as the chip of the device or on the same package as the package of the device is used.
With the technique in the related art, the recommended characteristic information related to a drive voltage range or a power source voltage fluctuation is written onto the non-volatile memory beforehand. A device manufacturer then reads the characteristic information written on the non-volatile memory through an outside terminal, and then individually adjusts the power source voltage in accordance with the characteristic information.